Senior Engineer, Design Verification Engineering

☞ Analog Devices

View: 105

Update day: 01-06-2024

Location: Newbury South East

Category: Architecture / Interior Design

Industry:

Job type: Full-time

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Job content

Analog Devices (NASDAQ: ADI) designs and manufactures semiconductor products and solutions. We enable our customers to interpret the world around us by intelligently bridging the physical and digital worlds with unmatched technologies that sense, measure and connect.
Verification Engineer

ADI’s Precision Converters Group is seeking Digital Verification Engineers to verify new integrated circuits and support assigned products through the full product life cycle.

Responsibilities
  • Acting as a senior verification team member or verification lead in a multi-disciplinary multi-site development team
  • Verification of interfaces, state machines, Digital Signal Processing, algorithms, controlling logic and other functions required to implement new converter products in a wide range of application spaces
  • Development of directed and constrained random test cases in SystemVerilog for verification of RTL and synthesised logic
  • Architecting, implementing, and/or managing complete metric-driven SystemVerilog and UVM verification environments.
  • Planning and scheduling of verification tasks and liaison with development team members
  • Presentation of architectures, methodologies and development progress at key milestones throughout the design cycle
  • Mentoring of junior engineers
  • Researching and developing new methods and processes of verification

Qualifications
  • Electronic Engineering/Computer Engineering/Electrical Engineering degree with 8+ years of experience in digital design verification
  • Should have a strong understanding and hands-on experience with System Verilog and UVM
  • Should be well versed with the typical verification cycle in IC design
  • Should have experience of verification plan development (functional coverage, checkers, testcases) from specification/standards
  • Should be able to develop a comprehensive UVM/SV testbench infrastructure (driver, monitor, scoreboard), including using Verification IP generated or developed externally
  • Experience of scan-testing and other Built-in self-test methods
  • Strong debugging and problem solving skills
  • Effective leadership and organisation skills; including leading a team spread across various sites, juggling responsibilities and managing temporary resources
  • Some knowledge of communication protocols like SPI, I2C and data converter architectures would be an advantage
  • Strong written and verbal communication skills, including technical presentations
  • Strong coding, object-oriented programming, and documentation skills
  • System Verilog Assertion for Dynamic and Formal Verification
  • Knowledge of and capability to execute the entire verification/design process and cover all verification metrics defined in the verification plan with minimal oversight and to schedule
  • Extensive experience with a scripting language (Python, C, Perl, etc.) would be an advantage
  • Mixed-signal simulation (for example Cadence AMS), interfacing with analog functions would be useful
  • Has demonstrated the ability to come up with innovative flows/techniques to aid verification quality and closure
  • Hands on experience on any advanced emulators like Palladium/Veloce/ZeBu would be an advantage
  • Exposure to a breadth of verification activities is desirable (Formal, power aware, FPGA, etc)
For positions requiring access to technical data, Analog Devices, Inc. may have to obtain export licensing approval from the U.S. Department of Commerce - Bureau of Industry and Security and/or the U.S. Department of State - Directorate of Defense Trade Controls. As such, applicants for this position – except US Citizens, US Permanent Residents, and protected individuals as defined by 8 U.S.C. 1324b(a)(3) – may have to go through an export licensing review process.
Analog Devices is an equal opportunity employer. We foster a culture where everyone has an opportunity to succeed regardless of their race, color, religion, age, ancestry, national origin, social or ethnic origin, sex, sexual orientation, gender, gender identity, gender expression, marital status, pregnancy, parental status, disability, medical condition, genetic information, military or veteran status, union membership, and political affiliation, or any other legally protected group.
Job Req Type: Experienced
Required Travel: Yes, 10% of the time
Shift Type: 1st Shift/Days
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Deadline: 16-07-2024

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