Design Verification Engineer - Power Management

Job content

Summary

At Apple, we work every single day to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet? Do you like changing the game?
We have an opportunity for a results-oriented and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique and exciting opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every day.
We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers.
The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology, and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.


Key Qualifications

Advanced knowledge of SystemVerilog and UVM

Experience developing scalable and portable test-benches

Experience with constrained random verification environments

Experience defining coverage space, writing coverage model, analyzing results

Experience with Assertion Based Verification

Knowledge of Object Oriented Programming

Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)

Experience with Python, Perl or TCL

Excellent communication and interpersonal skills combined with the ability to collaborate

Basic knowledge of mixed signal verification


Description

In this role you will develop verification plans in coordination with design leads and architects.
You’ll be responsible for building and maintaining verification test bench components and environments.
Generate directed and constrained random tests.
Run simulations and debug design and environment issues.
Build functional coverage points, analyze coverage, and improve test environment to target coverage holes.
Craft automated verification flows for block and chip level verification.
Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs.
Work with other block and core level engineers to ensure a flawless verification flow.


Education & Experience

MS/BS in Computer Science or Electrical Engineering or equivalent


Additional Requirements

Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.


Role Number: 200234172